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2.5D Silicon Interposers

IPDiA has been pioneering Silicon interposer platform since early 2000. With more than 100 million silicon interposers delivered in various markets, IPDiA is clearly recognized as a market leader. IPDiA interposer product is offering a huge variety of solutions, from basic 2D interposer to advanced 2.5D interposer with passive components built in the Silicon, in order to meet all your interposer requirements.

IPDiA 2.5D silicon interposer is the perfect solution for advanced packaging or interposer concepts. Copper Vias technology combined with the state of the art Integrated Passive Device technology provides a high level of integration and system performance improvements such as efficient decoupling, RF front end performances, etc.

Key Features

  • 2 metal layers on top and 1 at the bottom
  • Thickness 300m
  • Via minimum pitch 150 m
  • Via diameter of 75 m
  • Very low leakage currents
  • Integrated passive components
  • 250 nF/mm2 trench capacitors with high stability
    and low ESR
  • High quality factor inductors Q > 80 at 10 GHz
  • Polysilicon resistors with excellent matching

Key Benefits

  • Huge system size reduction
  • Perfect CTE matching
  • Bumping and flip-chip or die attach and wire bonding
  • Native redistribution and fan-out
  • Compliant with :
    • Organic platform (FR4, PCB, Flex, etc.)
    • Ceramic platform Package substrate
    • Glass platform
    • Metallic lead-frame platform

Via structure on Integrated Passive

Designation Value Comments
Die thickness 200m typ
Via diameter 75m
Via pitch 125m
Via density Max 64 Vias/mm
Via filling Copper
Max allowed current per via 100mA Limited by the measurement equipment
Isolation breakdown voltage > 200V
Serial resistivity per via < 10mΩ See curve for details < 10mΩ up to 65GHz
Serial inductor per via < 100pH See curve for details ~ 50pH up to 10GHz
Via-bulk isolation < 1pF
IPD generation PICSC Passive components such as high-density trench capacitors (80nF/mm MIM capacitors (80pF/mm)) resistors, and high-Q Cu inductor.

2.5D Silicon Interposer main characteristics

Electrical performance:

Series resistance of vias versus frequency
Parasitic Inductance of vias versus frequency
TSV - model parameters

Typical TSV's RLC
- RS < 0.5 Ω
- LS < 400 fH
- Cs < 200 fF
- G (isolation) < 4ᵉ-4S
S Parameter
  • 1dB attenuation on transmission freq ~ 20Ghz (GND on 1st neighboring via)
  • >20dB isolation VIA to 1st neighboring VIA @ 20Ghz

Results on through silicon vias with a 75 m diameter and a 300 m depth

Interposer with TSV
and Cu routing on the wafer backside
Submounts for lighting platform

- PICS2 Cu (Passive Integration generation)
- Top side with one -controller flipped + underfill (Jetting)
- Bottom side with one RF-die flipped + underfill (Jetting)
- WL-CSP Module with end 300 m Leadfree solder balls